diff --git a/Makefile b/Makefile index 85a8333..59a8e6e 100644 --- a/Makefile +++ b/Makefile @@ -6,7 +6,6 @@ OBJS = \ $K/start.o \ $K/console.o \ $K/printf.o \ - $K/uart.o \ $K/kalloc.o \ $K/spinlock.o \ $K/string.o \ diff --git a/kernel/uart.c b/kernel/uart.c deleted file mode 100644 index 8056142..0000000 --- a/kernel/uart.c +++ /dev/null @@ -1,166 +0,0 @@ -// -// low-level driver routines for 16550a UART. -// - -#include "types.h" -#include "param.h" -#include "memlayout.h" -#include "riscv.h" -#include "spinlock.h" -#include "proc.h" -#include "defs.h" - -// the UART control registers are memory-mapped -// at address UART0. this macro returns the -// address of one of the registers. -#define Reg(reg) ((volatile unsigned char *)(UART0 + reg)) - -// the UART control registers. -// some have different meanings for -// read vs write. -// see http://byterunner.com/16550.html -#define RHR 0 // receive holding register (for input bytes) -#define THR 0 // transmit holding register (for output bytes) -#define IER 1 // interrupt enable register -#define IER_RX_ENABLE (1 << 0) -#define IER_TX_ENABLE (1 << 1) -#define FCR 2 // FIFO control register -#define FCR_FIFO_ENABLE (1 << 0) -#define FCR_FIFO_CLEAR (3 << 1) // clear the content of the two FIFOs -#define ISR 2 // interrupt status register -#define LCR 3 // line control register -#define LCR_EIGHT_BITS (3 << 0) -#define LCR_BAUD_LATCH (1 << 7) // special mode to set baud rate -#define LSR 5 // line status register -#define LSR_RX_READY (1 << 0) // input is waiting to be read from RHR -#define LSR_TX_IDLE (1 << 5) // THR can accept another character to send - -#define ReadReg(reg) (*(Reg(reg))) -#define WriteReg(reg, v) (*(Reg(reg)) = (v)) - -// the transmit output buffer. -struct spinlock uart_tx_lock; -#define UART_TX_BUF_SIZE 32 -char uart_tx_buf[UART_TX_BUF_SIZE]; -uint64 uart_tx_w; // write next to uart_tx_buf[uart_tx_w % UART_TX_BUF_SIZE] -uint64 uart_tx_r; // read next from uart_tx_buf[uart_tx_r % UART_TX_BUF_SIZE] - -extern volatile int panicked; // from printf.c - -void uartstart(); - -void uartinit(void) { - // disable interrupts. - WriteReg(IER, 0x00); - - // special mode to set baud rate. - WriteReg(LCR, LCR_BAUD_LATCH); - - // LSB for baud rate of 38.4K. - WriteReg(0, 0x03); - - // MSB for baud rate of 38.4K. - WriteReg(1, 0x00); - - // leave set-baud mode, - // and set word length to 8 bits, no parity. - WriteReg(LCR, LCR_EIGHT_BITS); - - // reset and enable FIFOs. - WriteReg(FCR, FCR_FIFO_ENABLE | FCR_FIFO_CLEAR); - - // enable transmit and receive interrupts. - WriteReg(IER, IER_TX_ENABLE | IER_RX_ENABLE); - - initlock(&uart_tx_lock, "uart"); -} - -// add a character to the output buffer and tell the -// UART to start sending if it isn't already. -// blocks if the output buffer is full. -// because it may block, it can't be called -// from interrupts; it's only suitable for use -// by write(). -void uartputc(int c) { - acquire(&uart_tx_lock); - - if (panicked) { - for (;;) - ; - } - while (uart_tx_w == uart_tx_r + UART_TX_BUF_SIZE) { - // buffer is full. - // wait for uartstart() to open up space in the buffer. - sleep(&uart_tx_r, &uart_tx_lock); - } - uart_tx_buf[uart_tx_w % UART_TX_BUF_SIZE] = c; - uart_tx_w += 1; - uartstart(); - release(&uart_tx_lock); -} - -// alternate version of uartputc() that doesn't -// use interrupts, for use by kernel printf() and -// to echo characters. it spins waiting for the uart's -// output register to be empty. -void uartputc_sync(int c) { - push_off(); - - if (panicked) { - for (;;) - ; - } - - // wait for Transmit Holding Empty to be set in LSR. - while ((ReadReg(LSR) & LSR_TX_IDLE) == 0) - ; - WriteReg(THR, c); - - pop_off(); -} - -// if the UART is idle, and a character is waiting -// in the transmit buffer, send it. -// caller must hold uart_tx_lock. -// called from both the top- and bottom-half. -void uartstart() { - while (1) { - if (uart_tx_w == uart_tx_r) { - // transmit buffer is empty. - return; - } - - if ((ReadReg(LSR) & LSR_TX_IDLE) == 0) { - // the UART transmit holding register is full, - // so we cannot give it another byte. - // it will interrupt when it's ready for a new byte. - return; - } - - int c = uart_tx_buf[uart_tx_r % UART_TX_BUF_SIZE]; - uart_tx_r += 1; - - // maybe uartputc() is waiting for space in the buffer. - wakeup(&uart_tx_r); - - WriteReg(THR, c); - } -} - -// handle a uart interrupt, raised because input has -// arrived, or the uart is ready for more output, or -// both. called from devintr(). -void uartintr(void) { - // read and process incoming characters. - while (1) { - int c = uartgetc(); - if (c == -1) - break; - consoleintr(c); - } - - // send buffered characters. - acquire(&uart_tx_lock); - uartstart(); - release(&uart_tx_lock); -} diff --git a/theseus/src/lib.rs b/theseus/src/lib.rs index d3275d5..3c74574 100644 --- a/theseus/src/lib.rs +++ b/theseus/src/lib.rs @@ -3,6 +3,7 @@ pub mod memlayout; pub mod riscv; +pub mod spinlock; pub mod uart; #[panic_handler] diff --git a/theseus/src/spinlock.rs b/theseus/src/spinlock.rs new file mode 100644 index 0000000..faeafd0 --- /dev/null +++ b/theseus/src/spinlock.rs @@ -0,0 +1,9 @@ +// Mutual exclusion lock. +#[repr(C)] +pub struct SpinLock { + // Is the lock held? + pub locked: u32, // C boolean + // For debugging: + pub name: Option<*mut ()>, // Name of lock. + pub cpu: Option<*mut ()>, // The cpu holding the lock. +} diff --git a/theseus/src/uart.rs b/theseus/src/uart.rs index 81116cc..3477dca 100644 --- a/theseus/src/uart.rs +++ b/theseus/src/uart.rs @@ -1,4 +1,21 @@ -use crate::memlayout::UART0; +use crate::{memlayout::UART0, spinlock::SpinLock}; +use core::ptr::addr_of_mut; + +extern "C" { + // spinlock.c + fn push_off(); + fn pop_off(); + fn initlock(spinlock: *mut SpinLock, name: *const u8); + fn acquire(spinlock: *mut SpinLock); + fn release(spinlock: *mut SpinLock); + + // console.c + fn consoleintr(c: i32); + + // proc.c + fn sleep(chan: *const u64, spinlock: *mut SpinLock); + fn wakeup(chan: *const u64); +} // the UART control registers are memory-mapped // at address UART0. this macro returns the @@ -38,33 +55,143 @@ pub fn WriteReg(reg: u8, v: u8) { } // the transmit output buffer. -// static mut uart_tx_lock: crate::spinlock::SpinLock = crate::spinlock::SpinLock { locked: false }; +static mut uart_tx_lock: crate::spinlock::SpinLock = crate::spinlock::SpinLock { + locked: 0, + cpu: None, + name: None, +}; + +// NOTE: string 'uart\0' for c-implmentation of spinlock. Stupid but works. +static UART_LOCK_NAME: [u8; 5] = [117, 97, 114, 116, 0]; const UART_TX_BUF_SIZE: usize = 32; static mut uart_tx_buf: [u8; UART_TX_BUF_SIZE] = [0; UART_TX_BUF_SIZE]; static mut uart_tx_w: u64 = 0; // write next to uart_tx_buf[uart_tx_w % UART_TX_BUF_SIZE] static mut uart_tx_r: u64 = 0; // read next from uart_tx_buf[uart_tx_r % UART_TX_BUF_SIZE] -static mut panicked: i32 = 0; - -// #[no_mangle] -// pub extern "C" fn uartinit() {} - -// #[no_mangle] -// pub extern "C" fn uartintr() {} - -// #[no_mangle] -// pub extern "C" fn uartputc(c: i32) {} - -// #[no_mangle] -// pub extern "C" fn uartputc_sync(c: i32) {} +static mut panicked: bool = false; + +#[no_mangle] +pub extern "C" fn uartinit() { + // disable interrupts. + WriteReg(IER, 0x00); + + // special mode to set baud rate. + WriteReg(LCR, LCR_BAUD_LATCH); + + // LSB for baud rate of 38.4K. + WriteReg(0, 0x03); + + // MSB for baud rate of 38.4K. + WriteReg(1, 0x00); + + // leave set-baud mode, + // and set word length to 8 bits, no parity. + WriteReg(LCR, LCR_EIGHT_BITS); + + // reset and enable FIFOs. + WriteReg(FCR, FCR_FIFO_ENABLE | FCR_FIFO_CLEAR); + + // enable transmit and receive interrupts. + WriteReg(IER, IER_TX_ENABLE | IER_RX_ENABLE); + + unsafe { + initlock(addr_of_mut!(uart_tx_lock), UART_LOCK_NAME.as_ptr()); + } +} + +#[no_mangle] +pub extern "C" fn uartintr() { + // read and process incoming characters. + unsafe { + loop { + let c = uartgetc(); + if c == -1 { + break; + } + consoleintr(c); + } + + // send buffered characters. + acquire(addr_of_mut!(uart_tx_lock)); + uartstart(); + release(addr_of_mut!(uart_tx_lock)); + } +} + +#[no_mangle] +pub extern "C" fn uartputc(c: u8) { + unsafe { + acquire(addr_of_mut!(uart_tx_lock)); + + if panicked { + loop {} + } + while uart_tx_w == uart_tx_r + UART_TX_BUF_SIZE as u64 { + // buffer is full. + // wait for uartstart() to open up space in the buffer. + sleep(addr_of_mut!(uart_tx_r), addr_of_mut!(uart_tx_lock)); + } + uart_tx_buf[uart_tx_w as usize % UART_TX_BUF_SIZE] = c; + uart_tx_w += 1; + uartstart(); + release(addr_of_mut!(uart_tx_lock)); + } +} + +#[no_mangle] +pub extern "C" fn uartputc_sync(c: u8) { + unsafe { + push_off(); + + if panicked { + loop {} + } + + while ReadReg(LSR) & LSR_TX_IDLE == 0 {} + + WriteReg(THR, c); + + pop_off(); + } +} #[no_mangle] -// TODO: Convert to Option pub unsafe extern "C" fn uartgetc() -> i32 { + // TODO: Convert return type to Option if ReadReg(LSR) & 0x01 != 0 { ReadReg(RHR) as i32 } else { -1 } } + +// if the UART is idle, and a character is waiting +// in the transmit buffer, send it. +// caller must hold uart_tx_lock. +// called from both the top- and bottom-half. +fn uartstart() { + unsafe { + loop { + if uart_tx_w == uart_tx_r { + // transmit buffer is empty. + return; + } + + if (ReadReg(LSR) & LSR_TX_IDLE) == 0 { + // the UART transmit holding register is full, + // so we cannot give it another byte. + // it will interrupt when it's ready for a new byte. + return; + } + + let c: u8 = uart_tx_buf[uart_tx_r as usize % UART_TX_BUF_SIZE]; + uart_tx_r += 1; + + // maybe uartputc() is waiting for space in the buffer. + wakeup(addr_of_mut!(uart_tx_r)); + + WriteReg(THR, c); + } + } +}