hheik
/
xv6-riscv-rust
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Formatted *.h files

feat/start
hheik 2024-04-30 00:59:43 +03:00
parent d9faacecaf
commit 8d44d9c964
18 changed files with 555 additions and 649 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
kernel/buf.h
View File

@ -9,4 +9,3 @@ struct buf {
struct buf *next;
uchar data[BSIZE];
};

2
kernel/fs.h
View File

@ -1,7 +1,6 @@
// On-disk file system format.
// Both the kernel and user programs use this header file.
#define ROOTINO 1 // root i-number
#define BSIZE 1024 // block size
@ -57,4 +56,3 @@ struct dirent {
ushort inum;
char name[DIRSIZ];
};

4
kernel/main.c
View File

@ -3,9 +3,7 @@
#include "memlayout.h"
#include "riscv.h"
#include "defs.h"
#include <stdint.h>
extern int32_t add(int32_t right, int32_t left);
#include "rust.h"
volatile static int started = 0;

168
kernel/riscv.h
View File

@ -1,9 +1,7 @@
#ifndef __ASSEMBLER__
// which hart (core) is this?
static inline uint64
r_mhartid()
{
static inline uint64 r_mhartid() {
uint64 x;
asm volatile("csrr %0, mhartid" : "=r"(x));
return x;
@ -17,26 +15,20 @@ r_mhartid()
#define MSTATUS_MPP_U (0L << 11)
#define MSTATUS_MIE (1L << 3) // machine-mode interrupt enable.
static inline uint64
r_mstatus()
{
static inline uint64 r_mstatus() {
uint64 x;
asm volatile("csrr %0, mstatus" : "=r"(x));
return x;
}
static inline void
w_mstatus(uint64 x)
{
static inline void w_mstatus(uint64 x) {
asm volatile("csrw mstatus, %0" : : "r"(x));
}
// machine exception program counter, holds the
// instruction address to which a return from
// exception will go.
static inline void
w_mepc(uint64 x)
{
static inline void w_mepc(uint64 x) {
asm volatile("csrw mepc, %0" : : "r"(x));
}
@ -48,151 +40,107 @@ w_mepc(uint64 x)
#define SSTATUS_SIE (1L << 1) // Supervisor Interrupt Enable
#define SSTATUS_UIE (1L << 0) // User Interrupt Enable
static inline uint64
r_sstatus()
{
static inline uint64 r_sstatus() {
uint64 x;
asm volatile("csrr %0, sstatus" : "=r"(x));
return x;
}
static inline void
w_sstatus(uint64 x)
{
static inline void w_sstatus(uint64 x) {
asm volatile("csrw sstatus, %0" : : "r"(x));
}
// Supervisor Interrupt Pending
static inline uint64
r_sip()
{
static inline uint64 r_sip() {
uint64 x;
asm volatile("csrr %0, sip" : "=r"(x));
return x;
}
static inline void
w_sip(uint64 x)
{
asm volatile("csrw sip, %0" : : "r" (x));
}
static inline void w_sip(uint64 x) { asm volatile("csrw sip, %0" : : "r"(x)); }
// Supervisor Interrupt Enable
#define SIE_SEIE (1L << 9) // external
#define SIE_STIE (1L << 5) // timer
#define SIE_SSIE (1L << 1) // software
static inline uint64
r_sie()
{
static inline uint64 r_sie() {
uint64 x;
asm volatile("csrr %0, sie" : "=r"(x));
return x;
}
static inline void
w_sie(uint64 x)
{
asm volatile("csrw sie, %0" : : "r" (x));
}
static inline void w_sie(uint64 x) { asm volatile("csrw sie, %0" : : "r"(x)); }
// Machine-mode Interrupt Enable
#define MIE_MEIE (1L << 11) // external
#define MIE_MTIE (1L << 7) // timer
#define MIE_MSIE (1L << 3) // software
static inline uint64
r_mie()
{
static inline uint64 r_mie() {
uint64 x;
asm volatile("csrr %0, mie" : "=r"(x));
return x;
}
static inline void
w_mie(uint64 x)
{
asm volatile("csrw mie, %0" : : "r" (x));
}
static inline void w_mie(uint64 x) { asm volatile("csrw mie, %0" : : "r"(x)); }
// supervisor exception program counter, holds the
// instruction address to which a return from
// exception will go.
static inline void
w_sepc(uint64 x)
{
static inline void w_sepc(uint64 x) {
asm volatile("csrw sepc, %0" : : "r"(x));
}
static inline uint64
r_sepc()
{
static inline uint64 r_sepc() {
uint64 x;
asm volatile("csrr %0, sepc" : "=r"(x));
return x;
}
// Machine Exception Delegation
static inline uint64
r_medeleg()
{
static inline uint64 r_medeleg() {
uint64 x;
asm volatile("csrr %0, medeleg" : "=r"(x));
return x;
}
static inline void
w_medeleg(uint64 x)
{
static inline void w_medeleg(uint64 x) {
asm volatile("csrw medeleg, %0" : : "r"(x));
}
// Machine Interrupt Delegation
static inline uint64
r_mideleg()
{
static inline uint64 r_mideleg() {
uint64 x;
asm volatile("csrr %0, mideleg" : "=r"(x));
return x;
}
static inline void
w_mideleg(uint64 x)
{
static inline void w_mideleg(uint64 x) {
asm volatile("csrw mideleg, %0" : : "r"(x));
}
// Supervisor Trap-Vector Base Address
// low two bits are mode.
static inline void
w_stvec(uint64 x)
{
static inline void w_stvec(uint64 x) {
asm volatile("csrw stvec, %0" : : "r"(x));
}
static inline uint64
r_stvec()
{
static inline uint64 r_stvec() {
uint64 x;
asm volatile("csrr %0, stvec" : "=r"(x));
return x;
}
// Machine-mode interrupt vector
static inline void
w_mtvec(uint64 x)
{
static inline void w_mtvec(uint64 x) {
asm volatile("csrw mtvec, %0" : : "r"(x));
}
// Physical Memory Protection
static inline void
w_pmpcfg0(uint64 x)
{
static inline void w_pmpcfg0(uint64 x) {
asm volatile("csrw pmpcfg0, %0" : : "r"(x));
}
static inline void
w_pmpaddr0(uint64 x)
{
static inline void w_pmpaddr0(uint64 x) {
asm volatile("csrw pmpaddr0, %0" : : "r"(x));
}
@ -203,93 +151,65 @@ w_pmpaddr0(uint64 x)
// supervisor address translation and protection;
// holds the address of the page table.
static inline void
w_satp(uint64 x)
{
static inline void w_satp(uint64 x) {
asm volatile("csrw satp, %0" : : "r"(x));
}
static inline uint64
r_satp()
{
static inline uint64 r_satp() {
uint64 x;
asm volatile("csrr %0, satp" : "=r"(x));
return x;
}
static inline void
w_mscratch(uint64 x)
{
static inline void w_mscratch(uint64 x) {
asm volatile("csrw mscratch, %0" : : "r"(x));
}
// Supervisor Trap Cause
static inline uint64
r_scause()
{
static inline uint64 r_scause() {
uint64 x;
asm volatile("csrr %0, scause" : "=r"(x));
return x;
}
// Supervisor Trap Value
static inline uint64
r_stval()
{
static inline uint64 r_stval() {
uint64 x;
asm volatile("csrr %0, stval" : "=r"(x));
return x;
}
// Machine-mode Counter-Enable
static inline void
w_mcounteren(uint64 x)
{
static inline void w_mcounteren(uint64 x) {
asm volatile("csrw mcounteren, %0" : : "r"(x));
}
static inline uint64
r_mcounteren()
{
static inline uint64 r_mcounteren() {
uint64 x;
asm volatile("csrr %0, mcounteren" : "=r"(x));
return x;
}
// machine-mode cycle counter
static inline uint64
r_time()
{
static inline uint64 r_time() {
uint64 x;
asm volatile("csrr %0, time" : "=r"(x));
return x;
}
// enable device interrupts
static inline void
intr_on()
{
w_sstatus(r_sstatus() | SSTATUS_SIE);
}
static inline void intr_on() { w_sstatus(r_sstatus() | SSTATUS_SIE); }
// disable device interrupts
static inline void
intr_off()
{
w_sstatus(r_sstatus() & ~SSTATUS_SIE);
}
static inline void intr_off() { w_sstatus(r_sstatus() & ~SSTATUS_SIE); }
// are device interrupts enabled?
static inline int
intr_get()
{
static inline int intr_get() {
uint64 x = r_sstatus();
return (x & SSTATUS_SIE) != 0;
}
static inline uint64
r_sp()
{
static inline uint64 r_sp() {
uint64 x;
asm volatile("mv %0, sp" : "=r"(x));
return x;
@ -297,32 +217,22 @@ r_sp()
// read and write tp, the thread pointer, which xv6 uses to hold
// this core's hartid (core number), the index into cpus[].
static inline uint64
r_tp()
{
static inline uint64 r_tp() {
uint64 x;
asm volatile("mv %0, tp" : "=r"(x));
return x;
}
static inline void
w_tp(uint64 x)
{
asm volatile("mv tp, %0" : : "r" (x));
}
static inline void w_tp(uint64 x) { asm volatile("mv tp, %0" : : "r"(x)); }
static inline uint64
r_ra()
{
static inline uint64 r_ra() {
uint64 x;
asm volatile("mv %0, ra" : "=r"(x));
return x;
}
// flush the TLB.
static inline void
sfence_vma()
{
static inline void sfence_vma() {
// the zero, zero means flush all TLB entries.
asm volatile("sfence.vma zero, zero");
}

1
kernel/sleeplock.h
View File

@ -7,4 +7,3 @@ struct sleeplock {
char *name; // Name of lock.
int pid; // Process holding lock
};

1
kernel/spinlock.h
View File

@ -6,4 +6,3 @@ struct spinlock {
char *name; // Name of lock.
struct cpu *cpu; // The cpu holding the lock.
};

9
kernel/virtio.h
View File

@ -23,11 +23,14 @@
#define VIRTIO_MMIO_INTERRUPT_STATUS 0x060 // read-only
#define VIRTIO_MMIO_INTERRUPT_ACK 0x064 // write-only
#define VIRTIO_MMIO_STATUS 0x070 // read/write
#define VIRTIO_MMIO_QUEUE_DESC_LOW 0x080 // physical address for descriptor table, write-only
#define VIRTIO_MMIO_QUEUE_DESC_LOW \
0x080 // physical address for descriptor table, write-only
#define VIRTIO_MMIO_QUEUE_DESC_HIGH 0x084
#define VIRTIO_MMIO_DRIVER_DESC_LOW 0x090 // physical address for available ring, write-only
#define VIRTIO_MMIO_DRIVER_DESC_LOW \
0x090 // physical address for available ring, write-only
#define VIRTIO_MMIO_DRIVER_DESC_HIGH 0x094
#define VIRTIO_MMIO_DEVICE_DESC_LOW 0x0a0 // physical address for used ring, write-only
#define VIRTIO_MMIO_DEVICE_DESC_LOW \
0x0a0 // physical address for used ring, write-only
#define VIRTIO_MMIO_DEVICE_DESC_HIGH 0x0a4
// status register bits, from qemu virtio_config.h