93 lines
2.6 KiB
Rust
93 lines
2.6 KiB
Rust
use core::arch::asm;
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use core::usize;
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use crate::kmain::kmain;
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use crate::memlayout::{CLINT_MTIME, CLINT_MTIMECMP};
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use crate::param::NCPU;
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use crate::riscv as rv;
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extern "C" {
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// assembly code in kernelvec.S for machine-mode timer interrupt.
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fn timervec();
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}
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#[repr(align(16))]
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pub struct EntryStack([u8; 4096 * NCPU]);
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// entry.S needs one stack per CPU.
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#[no_mangle]
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pub static mut stack0: EntryStack = EntryStack([0; 4096 * NCPU]);
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// a scratch area per CPU for machine-mode timer interrupts.
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static mut timer_scratch: [[u64; 5]; NCPU] = [[0; 5]; NCPU];
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// entry.S jumps here in machine mode on stack0.
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#[no_mangle]
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pub unsafe extern "C" fn start() {
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// set M Previous Privilege mode to Supervisor, for mret.
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let mut x = rv::r_mstatus();
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x &= !rv::MSTATUS_MPP_MASK;
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x |= rv::MSTATUS_MPP_S;
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rv::w_mstatus(x);
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// set M Exception Program Counter to main, for mret.
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// requires gcc -mcmodel=medany
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rv::w_mepc(kmain as *const () as u64);
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// disable paging for now.
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rv::w_satp(0);
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// delegate all interrupts and exceptions to supervisor mode.
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rv::w_medeleg(0xffff);
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rv::w_mideleg(0xffff);
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rv::w_sie(rv::r_sie() | rv::SIE_SEIE | rv::SIE_STIE | rv::SIE_SSIE);
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// configure Physical Memory Protection to give supervisor mode
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// access to all of physical memory.
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rv::w_pmpaddr0(0x3fffffffffffff);
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rv::w_pmpcfg0(0xf);
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// ask for clock interrupts.
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timerinit();
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// keep each CPU's hartid in its tp register, for cpuid().
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let id = rv::r_mhartid();
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rv::w_tp(id);
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// switch to supervisor mode and jump to main().
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asm!("mret");
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}
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// arrange to receive timer interrupts.
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// they will arrive in machine mode at
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// at timervec in kernelvec.S,
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// which turns them into software interrupts for
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// devintr() in trap.c.
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unsafe fn timerinit() {
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// each CPU has a separate source of timer interrupts.
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let id = rv::r_mhartid();
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// ask the CLINT for a timer interrupt.
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let interval: u64 = 1000000; // cycles; about 1/10th second in qemu.
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*CLINT_MTIMECMP(id) = *CLINT_MTIME + interval;
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// prepare information in scratch[] for timervec.
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// scratch[0..2] : space for timervec to save registers.
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// scratch[3] : address of CLINT MTIMECMP register.
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// scratch[4] : desired interval (in cycles) between timer interrupts.
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timer_scratch[id as usize][3] = CLINT_MTIMECMP(id) as u64;
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timer_scratch[id as usize][4] = interval;
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// w_mscratch((uint64)scratch);
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rv::w_mscratch(timer_scratch[id as usize].as_ptr() as u64);
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// set the machine-mode trap handler.
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rv::w_mtvec(timervec as *const () as u64);
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// enable machine-mode interrupts.
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rv::w_mstatus(rv::r_mstatus() | rv::MSTATUS_MIE);
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// enable machine-mode timer interrupts.
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rv::w_mie(rv::r_mie() | rv::MIE_MTIE);
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}
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