entry.S jumps to rust implementation of start()
hheik
parent
d57cdc9d6c
commit
cf55a8faa1
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@ -5,8 +5,8 @@
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.section .text
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.global _entry
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_entry:
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# set up a stack for C.
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# stack0 is declared in start.c,
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# set up a stack for Rust
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# stack0 is declared in start.rs,
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# with a 4096-byte stack per CPU.
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# sp = stack0 + (hartid * 4096)
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la sp, stack0
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@ -15,7 +15,7 @@ _entry:
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addi a1, a1, 1
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mul a0, a0, a1
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add sp, sp, a0
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# jump to start() in start.c
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# jump to start() in start.rs
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call start
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spin:
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j spin
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@ -4,54 +4,14 @@
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#include "riscv.h"
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#include "defs.h"
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void main();
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void timerinit();
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// entry.S needs one stack per CPU.
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__attribute__((aligned(16))) char stack0[4096 * NCPU];
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// a scratch area per CPU for machine-mode timer interrupts.
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uint64 timer_scratch[NCPU][5];
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// assembly code in kernelvec.S for machine-mode timer interrupt.
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extern void timervec();
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// entry.S jumps here in machine mode on stack0.
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void start() {
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// set M Previous Privilege mode to Supervisor, for mret.
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unsigned long x = r_mstatus();
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x &= ~MSTATUS_MPP_MASK;
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x |= MSTATUS_MPP_S;
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w_mstatus(x);
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// set M Exception Program Counter to main, for mret.
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// requires gcc -mcmodel=medany
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w_mepc((uint64)main);
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// disable paging for now.
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w_satp(0);
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// delegate all interrupts and exceptions to supervisor mode.
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w_medeleg(0xffff);
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w_mideleg(0xffff);
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w_sie(r_sie() | SIE_SEIE | SIE_STIE | SIE_SSIE);
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// configure Physical Memory Protection to give supervisor mode
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// access to all of physical memory.
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w_pmpaddr0(0x3fffffffffffffull);
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w_pmpcfg0(0xf);
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// ask for clock interrupts.
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timerinit();
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// keep each CPU's hartid in its tp register, for cpuid().
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int id = r_mhartid();
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w_tp(id);
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// switch to supervisor mode and jump to main().
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asm volatile("mret");
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}
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// arrange to receive timer interrupts.
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// they will arrive in machine mode at
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// at timervec in kernelvec.S,
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@ -2,8 +2,10 @@
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#![crate_type = "staticlib"]
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pub mod memlayout;
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pub mod param;
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pub mod riscv;
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pub mod spinlock;
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pub mod start;
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pub mod uart;
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extern "C" {
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@ -0,0 +1,13 @@
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pub const NPROC: usize = 64; // maximum number of processes
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pub const NCPU: usize = 8; // maximum number of CPUs
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pub const NOFILE: usize = 16; // open files per process
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pub const NFILE: usize = 100; // open files per system
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pub const NINODE: usize = 50; // maximum number of active i-nodes
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pub const NDEV: usize = 10; // maximum major device number
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pub const ROOTDEV: usize = 1; // device number of file system root disk
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pub const MAXARG: usize = 32; // max exec arguments
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pub const MAXOPBLOCKS: usize = 10; // max # of blocks any FS op writes
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pub const LOGSIZE: usize = MAXOPBLOCKS * 3; // max data blocks in on-disk log
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pub const NBUF: usize = MAXOPBLOCKS * 3; // size of disk block cache
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pub const FSSIZE: usize = 2000; // size of file system in blocks
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pub const MAXPATH: usize = 128; // maximum file path name
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@ -1,3 +1,290 @@
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use core::arch::asm;
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// which hart (core) is this?
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#[inline]
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pub unsafe fn r_mhartid() -> u64 {
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let x: u64;
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asm!("csrr {x}, mhartid", x = out(reg) x);
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x
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}
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// Machine Status Register, mstatus
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pub const MSTATUS_MPP_MASK: u64 = 3 << 11; // previous mode.
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pub const MSTATUS_MPP_M: u64 = 3 << 11;
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pub const MSTATUS_MPP_S: u64 = 1 << 11;
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pub const MSTATUS_MPP_U: u64 = 0 << 11;
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pub const MSTATUS_MIE: u64 = 1 << 3; // machine-mode interrupt enable.
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#[inline]
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pub unsafe fn r_mstatus() -> u64 {
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let x: u64;
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asm!("csrr {x}, mstatus", x = out(reg) x);
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x
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}
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#[inline]
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pub unsafe fn w_mstatus(x: u64) {
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asm!("csrw mstatus, {x}", x = in(reg) x);
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}
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// // machine exception program counter, holds the
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// // instruction address to which a return from
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// // exception will go.
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#[inline]
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pub unsafe fn w_mepc(x: u64) {
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asm!("csrw mepc, {x}", x = in(reg) x);
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}
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// // Supervisor Status Register, sstatus
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// #define SSTATUS_SPP (1L << 8) // Previous mode, 1=Supervisor, 0=User
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// #define SSTATUS_SPIE (1L << 5) // Supervisor Previous Interrupt Enable
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// #define SSTATUS_UPIE (1L << 4) // User Previous Interrupt Enable
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// #define SSTATUS_SIE (1L << 1) // Supervisor Interrupt Enable
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// #define SSTATUS_UIE (1L << 0) // User Interrupt Enable
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#[inline]
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pub unsafe fn r_sstatus() -> u64 {
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let x: u64;
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asm!("csrr {x}, sstatus", x = out(reg) x);
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x
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}
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#[inline]
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pub unsafe fn w_sstatus(x: u64) {
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asm!("csrw sstatus, {x}", x = in(reg) x);
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}
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// // Supervisor Interrupt Pending
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#[inline]
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pub unsafe fn r_sip() -> u64 {
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let x: u64;
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asm!("csrr {x}, sip", x = out(reg) x);
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x
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}
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// static inline void w_sip(uint64 x) { asm volatile("csrw sip, %0" : : "r"(x)); }
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#[inline]
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pub unsafe fn w_sip(x: u64) {
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asm!("csrw sip, {x}", x = in(reg) x);
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}
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// Supervisor Interrupt Enable
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pub const SIE_SEIE: u64 = 1 << 9; // external
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pub const SIE_STIE: u64 = 1 << 5; // timer
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pub const SIE_SSIE: u64 = 1 << 1; // software
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// static inline uint64 r_sie() {
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// uint64 x;
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// asm volatile("csrr %0, sie" : "=r"(x));
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// return x;
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// }
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#[inline]
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pub unsafe fn r_sie() -> u64 {
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let x: u64;
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asm!("csrr {x}, sie", x = out(reg) x);
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x
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}
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// static inline void w_sie(uint64 x) { asm volatile("csrw sie, %0" : : "r"(x)); }
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#[inline]
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pub unsafe fn w_sie(x: u64) {
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asm!("csrw sie, {x}", x = in(reg) x);
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}
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// // Machine-mode Interrupt Enable
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// #define MIE_MEIE (1L << 11) // external
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// #define MIE_MTIE (1L << 7) // timer
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// #define MIE_MSIE (1L << 3) // software
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// static inline uint64 r_mie() {
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// uint64 x;
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// asm volatile("csrr %0, mie" : "=r"(x));
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// return x;
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// }
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// static inline void w_mie(uint64 x) { asm volatile("csrw mie, %0" : : "r"(x)); }
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// // supervisor exception program counter, holds the
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// // instruction address to which a return from
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// // exception will go.
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// static inline void w_sepc(uint64 x) {
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// asm volatile("csrw sepc, %0" : : "r"(x));
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// }
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// static inline uint64 r_sepc() {
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// uint64 x;
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// asm volatile("csrr %0, sepc" : "=r"(x));
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// return x;
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// }
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// // Machine Exception Delegation
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// static inline uint64 r_medeleg() {
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// uint64 x;
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// asm volatile("csrr %0, medeleg" : "=r"(x));
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// return x;
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// }
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// static inline void w_medeleg(uint64 x) {
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// asm volatile("csrw medeleg, %0" : : "r"(x));
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// }
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#[inline]
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pub unsafe fn w_medeleg(x: u64) {
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asm!("csrw medeleg, {x}", x = in(reg) x);
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}
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// // Machine Interrupt Delegation
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// static inline uint64 r_mideleg() {
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// uint64 x;
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// asm volatile("csrr %0, mideleg" : "=r"(x));
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// return x;
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// }
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// static inline void w_mideleg(uint64 x) {
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// asm volatile("csrw mideleg, %0" : : "r"(x));
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// }
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#[inline]
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pub unsafe fn w_mideleg(x: u64) {
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asm!("csrw mideleg, {x}", x = in(reg) x);
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}
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// // Supervisor Trap-Vector Base Address
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// // low two bits are mode.
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// static inline void w_stvec(uint64 x) {
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// asm volatile("csrw stvec, %0" : : "r"(x));
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// }
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// static inline uint64 r_stvec() {
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// uint64 x;
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// asm volatile("csrr %0, stvec" : "=r"(x));
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// return x;
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// }
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// // Machine-mode interrupt vector
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// static inline void w_mtvec(uint64 x) {
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// asm volatile("csrw mtvec, %0" : : "r"(x));
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// }
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// // Physical Memory Protection
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// static inline void w_pmpcfg0(uint64 x) {
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// asm volatile("csrw pmpcfg0, %0" : : "r"(x));
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// }
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#[inline]
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pub unsafe fn w_pmpcfg0(x: u64) {
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asm!("csrw pmpcfg0, {x}", x = in(reg) x);
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}
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// static inline void w_pmpaddr0(uint64 x) {
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// asm volatile("csrw pmpaddr0, %0" : : "r"(x));
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// }
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#[inline]
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pub unsafe fn w_pmpaddr0(x: u64) {
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asm!("csrw pmpaddr0, {x}", x = in(reg) x);
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}
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// // use riscv's sv39 page table scheme.
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// #define SATP_SV39 (8L << 60)
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// #define MAKE_SATP(pagetable) (SATP_SV39 | (((uint64)pagetable) >> 12))
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// // supervisor address translation and protection;
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// // holds the address of the page table.
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// static inline void w_satp(uint64 x) {
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// asm volatile("csrw satp, %0" : : "r"(x));
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// }
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#[inline]
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pub unsafe fn w_satp(x: u64) {
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asm!("csrw satp, {x}", x = in(reg) x);
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}
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// static inline uint64 r_satp() {
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// uint64 x;
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// asm volatile("csrr %0, satp" : "=r"(x));
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// return x;
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// }
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// static inline void w_mscratch(uint64 x) {
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// asm volatile("csrw mscratch, %0" : : "r"(x));
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// }
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// // Supervisor Trap Cause
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// static inline uint64 r_scause() {
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// uint64 x;
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// asm volatile("csrr %0, scause" : "=r"(x));
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// return x;
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// }
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// // Supervisor Trap Value
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// static inline uint64 r_stval() {
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// uint64 x;
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// asm volatile("csrr %0, stval" : "=r"(x));
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// return x;
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// }
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// // Machine-mode Counter-Enable
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// static inline void w_mcounteren(uint64 x) {
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// asm volatile("csrw mcounteren, %0" : : "r"(x));
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// }
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// static inline uint64 r_mcounteren() {
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// uint64 x;
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// asm volatile("csrr %0, mcounteren" : "=r"(x));
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// return x;
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// }
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// // machine-mode cycle counter
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// static inline uint64 r_time() {
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// uint64 x;
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// asm volatile("csrr %0, time" : "=r"(x));
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// return x;
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// }
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// // enable device interrupts
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// static inline void intr_on() { w_sstatus(r_sstatus() | SSTATUS_SIE); }
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// // disable device interrupts
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// static inline void intr_off() { w_sstatus(r_sstatus() & ~SSTATUS_SIE); }
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// // are device interrupts enabled?
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// static inline int intr_get() {
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// uint64 x = r_sstatus();
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// return (x & SSTATUS_SIE) != 0;
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// }
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// static inline uint64 r_sp() {
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// uint64 x;
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// asm volatile("mv %0, sp" : "=r"(x));
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// return x;
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// }
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// // read and write tp, the thread pointer, which xv6 uses to hold
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// // this core's hartid (core number), the index into cpus[].
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// static inline uint64 r_tp() {
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// uint64 x;
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// asm volatile("mv %0, tp" : "=r"(x));
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// return x;
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// }
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// static inline void w_tp(uint64 x) { asm volatile("mv tp, %0" : : "r"(x)); }
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#[inline]
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pub unsafe fn w_tp(x: u64) {
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asm!("mv tp, {x}", x = in(reg) x);
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}
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// static inline uint64 r_ra() {
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// uint64 x;
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// asm volatile("mv %0, ra" : "=r"(x));
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// return x;
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// }
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// // flush the TLB.
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// static inline void sfence_vma() {
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// // the zero, zero means flush all TLB entries.
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// asm volatile("sfence.vma zero, zero");
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// }
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// typedef uint64 pte_t;
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// typedef uint64 *pagetable_t; // 512 PTEs
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pub const PGSIZE: u64 = 4096; // bytes per page
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pub const PGSHIFT: i32 = 12; // bits of offset within a page
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@ -0,0 +1,54 @@
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use core::arch::asm;
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use crate::param::NCPU;
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use crate::riscv as rv;
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extern "C" {
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// start.c
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fn timerinit();
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// main.c
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fn main();
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}
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#[repr(align(16))]
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pub struct AlignedStack([u8; 4096 * NCPU]);
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#[no_mangle]
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pub static mut stack0: AlignedStack = AlignedStack([0; 4096 * NCPU]);
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// entry.S jumps here in machine mode on stack0.
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#[no_mangle]
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pub unsafe extern "C" fn start() {
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// set M Previous Privilege mode to Supervisor, for mret.
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let mut x = rv::r_mstatus();
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x &= !rv::MSTATUS_MPP_MASK;
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x |= rv::MSTATUS_MPP_S;
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rv::w_mstatus(x);
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// set M Exception Program Counter to main, for mret.
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// requires gcc -mcmodel=medany
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rv::w_mepc(main as *const () as u64);
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// disable paging for now.
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rv::w_satp(0);
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// delegate all interrupts and exceptions to supervisor mode.
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rv::w_medeleg(0xffff);
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rv::w_mideleg(0xffff);
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rv::w_sie(rv::r_sie() | rv::SIE_SEIE | rv::SIE_STIE | rv::SIE_SSIE);
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// configure Physical Memory Protection to give supervisor mode
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// access to all of physical memory.
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rv::w_pmpaddr0(0x3fffffffffffff);
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rv::w_pmpcfg0(0xf);
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// ask for clock interrupts.
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timerinit();
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// keep each CPU's hartid in its tp register, for cpuid().
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let id = rv::r_mhartid();
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rv::w_tp(id);
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// switch to supervisor mode and jump to main().
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asm!("mret");
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}
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