xv6-riscv-rust/theseus/src/uart.rs

use crate::{
	memlayout::UART0,
	spinlock::{initlock, SpinLock},
};
use core::ptr::{addr_of_mut, null, null_mut};

extern "C" {
	// spinlock.c
	fn push_off();
	fn pop_off();
	fn acquire(spinlock: *mut SpinLock);
	fn release(spinlock: *mut SpinLock);

	// console.c
	fn consoleintr(c: i32);

	// proc.c
	fn sleep(chan: *const u64, spinlock: *mut SpinLock);
	fn wakeup(chan: *const u64);

	//printf.c
	static mut panicked: bool;
}

// the UART control registers are memory-mapped
// at address UART0. this macro returns the
// address of one of the registers.
#[inline]
pub fn Reg(reg: u8) -> *mut u8 {
	(UART0 + reg as u64) as *mut u8
}

// the UART control registers.
// some have different meanings for
// read vs write.
// see http://byterunner.com/16550.html
const RHR: u8 = 0; // receive holding register (for input bytes)
const THR: u8 = 0; // transmit holding register (for output bytes)
const IER: u8 = 1; // interrupt enable register
const IER_RX_ENABLE: u8 = 1 << 0;
const IER_TX_ENABLE: u8 = 1 << 1;
const FCR: u8 = 2; // FIFO control register
const FCR_FIFO_ENABLE: u8 = 1 << 0;
const FCR_FIFO_CLEAR: u8 = 3 << 1; // clear the content of the two FIFOs
const ISR: u8 = 2; // interrupt status register
const LCR: u8 = 3; // line control register
const LCR_EIGHT_BITS: u8 = 3 << 0;
const LCR_BAUD_LATCH: u8 = 1 << 7; // special mode to set baud rate
const LSR: u8 = 5; // line status register
const LSR_RX_READY: u8 = 1 << 0; // input is waiting to be read from RHR
const LSR_TX_IDLE: u8 = 1 << 5; // THR can accept another character to send

#[inline]
pub fn ReadReg(reg: u8) -> u8 {
	unsafe { *Reg(reg) }
}
#[inline]
pub fn WriteReg(reg: u8, v: u8) {
	unsafe { *Reg(reg) = v }
}

// the transmit output buffer.
static mut uart_tx_lock: crate::spinlock::SpinLock = crate::spinlock::SpinLock {
	locked: 0,
	cpu: null_mut(),
	name: null(),
};

// NOTE: string 'uart\0' for c-implmentation of spinlock. Stupid but works.
static UART_LOCK_NAME: [u8; 5] = [0x75, 0x61, 0x72, 0x74, 0];

const UART_TX_BUF_SIZE: usize = 32;
static mut uart_tx_buf: [u8; UART_TX_BUF_SIZE] = [0; UART_TX_BUF_SIZE];
static mut uart_tx_w: u64 = 0; // write next to uart_tx_buf[uart_tx_w % UART_TX_BUF_SIZE]
static mut uart_tx_r: u64 = 0; // read next from uart_tx_buf[uart_tx_r % UART_TX_BUF_SIZE]

#[no_mangle]
pub extern "C" fn uartinit() {
	// disable interrupts.
	WriteReg(IER, 0x00);

	// special mode to set baud rate.
	WriteReg(LCR, LCR_BAUD_LATCH);

	// LSB for baud rate of 38.4K.
	WriteReg(0, 0x03);

	// MSB for baud rate of 38.4K.
	WriteReg(1, 0x00);

	// leave set-baud mode,
	// and set word length to 8 bits, no parity.
	WriteReg(LCR, LCR_EIGHT_BITS);

	// reset and enable FIFOs.
	WriteReg(FCR, FCR_FIFO_ENABLE | FCR_FIFO_CLEAR);

	// enable transmit and receive interrupts.
	WriteReg(IER, IER_TX_ENABLE | IER_RX_ENABLE);

	unsafe {
		initlock(addr_of_mut!(uart_tx_lock), UART_LOCK_NAME.as_ptr());
	}
}

#[no_mangle]
pub extern "C" fn uartintr() {
	// read and process incoming characters.
	unsafe {
		loop {
			let c = uartgetc();
			if c == -1 {
				break;
			}
			consoleintr(c);
		}

		// send buffered characters.
		acquire(addr_of_mut!(uart_tx_lock));
		uartstart();
		release(addr_of_mut!(uart_tx_lock));
	}
}

#[no_mangle]
pub extern "C" fn uartputc(c: u8) {
	unsafe {
		acquire(addr_of_mut!(uart_tx_lock));

		if panicked {
			loop {}
		}
		while uart_tx_w == uart_tx_r + UART_TX_BUF_SIZE as u64 {
			// buffer is full.
			// wait for uartstart() to open up space in the buffer.
			sleep(addr_of_mut!(uart_tx_r), addr_of_mut!(uart_tx_lock));
		}
		uart_tx_buf[uart_tx_w as usize % UART_TX_BUF_SIZE] = c;
		uart_tx_w += 1;
		uartstart();
		release(addr_of_mut!(uart_tx_lock));
	}
}

#[no_mangle]
pub extern "C" fn uartputc_sync(c: u8) {
	unsafe {
		push_off();

		if panicked {
			loop {}
		}

		while ReadReg(LSR) & LSR_TX_IDLE == 0 {}

		WriteReg(THR, c);

		pop_off();
	}
}

#[no_mangle]
pub unsafe extern "C" fn uartgetc() -> i32 {
	// TODO: Convert return type to Option<u8>
	if ReadReg(LSR) & 0x01 != 0 {
		ReadReg(RHR) as i32
	} else {
		-1
	}
}

// if the UART is idle, and a character is waiting
// in the transmit buffer, send it.
// caller must hold uart_tx_lock.
// called from both the top- and bottom-half.
fn uartstart() {
	unsafe {
		loop {
			if uart_tx_w == uart_tx_r {
				// transmit buffer is empty.
				return;
			}

			if (ReadReg(LSR) & LSR_TX_IDLE) == 0 {
				// the UART transmit holding register is full,
				// so we cannot give it another byte.
				// it will interrupt when it's ready for a new byte.
				return;
			}

			let c: u8 = uart_tx_buf[uart_tx_r as usize % UART_TX_BUF_SIZE];
			uart_tx_r += 1;

			// maybe uartputc() is waiting for space in the buffer.
			wakeup(addr_of_mut!(uart_tx_r));

			WriteReg(THR, c);
		}
	}
}